`timescale 1ns / 1ps

module mod48_tb();

reg Clk;
reg Reset_n;
wire [7:0]Q;
wire clock;
wire sh_cp;
wire st_cp;
wire ds;

defparam mod48_inst0.MCNT=12_499;

mod48 mod48_inst0(
.Clk(Clk),
.Reset_n(Reset_n),
.Q(Q),
.clock(clock),
.sh_cp(sh_cp),
.st_cp(st_cp),
.ds(ds)
);

initial Clk=0;
always #10 Clk=~Clk;

initial begin
Reset_n=0;
#201;
Reset_n=1;
#26000000;
$stop;
end

endmodule
